MC100EP139DTR2G Clock & Data Distribution by ON Semiconductor

3.3 V / 5.0 V ECL ÷·2/4, ÷·4/5/6 Clock Generator Chip

Semiconductors - ICs
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Status: Active
Series: MC100EP139
RoHS: Compliant
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The MC10/100EP139 is a low skew divide by 2/4, divide by 4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, LVPECL input signals. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLKbar input and bypassed to ground via a 0.01uF capacitor. The common enable (ENbar) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon startup, the internal flip-flops will attain a random state; therefore, for systems which utilize multiple EP139s, the master reset (MR) input must be asserted to ensure synchronization. For systems which only use one EP139, the MR pin need not be exercised as the internal divider design ensures synchronization between the divide by 2/4 and the divide by 4/5/6 outputs of a single device. All VCC and VEE pins must be externally connected to power supply to guarantee proper operation. The 100 Series contains temperature compensation.

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Prices starting from US$11.33

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Features

Maximum Frequency >1.0 GHz Typical
50ps Output-to-Output Skew
PECL Mode Operating Range: VCC=3.0 V to 5.5 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
Open Input Default State
Safety Clamp on Inputs
Synchronous Enable/Disable
Master Reset for Synchronization of Multiple Chips
VBB Output
Pb-Free Packages are Available
Applications
Low-Clock Skew Generation

Specifications

Description MC100EP139
Compliance Pb-free Halide free
Type Divider
Input Level CML ECL
Output Level ECL
VCC Typ (V) 3.3 5
fMax Typ (MHz) 1000
tpd Typ (ns) 0.75
tR & tF Max (ps) 250
Package Type TSSOP-20

Last 6 months Inventory & Pricing History

Alternative Descriptions

Clock Generator, 1Ghz, -40 To 85Deg C | Newark Electronics
MC100EP139 Series 1 GHz 5.5 V ECL ÷2/4, ÷4/5/6 Clock Generation Chip - TSSOP-20 | Future Electronics
IC: digital | TME
CLOCK GENERATOR, 1GHZ, -40 TO 85DEG C | Farnell

Frequently Asked Questions

Where can I find additional details, specifications and documents for a MC100EP139DTR2G?

Additional datasheets, footprints and schematics for MC100EP139DTR2G are listed on our Part Details page. You can also find images and similar parts to MC100EP139DTR2G on this page.

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What category does MC100EP139DTR2G fall under?

The MC100EP139DTR2G is listed under Timing, Logic & Memory > Clock & Data Distribution > Arithmetic Functions.

Can I view similar or alternative parts?

You can view similar parts to MC100EP139DTR2G when available in the Arithmetic Functions range under the specifications section at the bottom of the details page.

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Is the MC100EP139DTR2G RoHS compliant?

Yes. This part has been flagged as RoHS Compliant by ON Semiconductor.

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Authorised distributors including Newark Electronics, Future Electronics, TME, Farnell and Avnet Silica have stock available or on a lead time for MC100EP139DTR2G.

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