MC100LVEL39DWR2G Clock & Data Distribution by ON Semiconductor

3.3 V ECL ÷·2/4, ÷·4/6 Clock Generation Chip

Semiconductors - ICs
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Status: Active
Series: MC100LVEL39
RoHS: Compliant
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The MC100LVEL39 is a low skew 2/4, 4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended input signal. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device. The common enable (ENbar) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon startup, the internal flip-flops will attain a random state; therefore, for systems which utilize multiple LVEL39s, the master reset (MR) input must be asserted to ensure synchronization. For systems which only use one LVEL39, the MR pin need not be exercised as the internal divider design ensures synchronization between the 2/4 and the 4/6 outputs of a single device. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

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Features

50 ps Maximum Output-to-Output Skew
Synchronous Enable/Disable
Master Reset for Synchronization
ESD Protection: >2 KV HBM
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.8 V
Internal Input Pulldown Resistors
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
Transistor Count = 419 devices
Pb-Free Packages are Available

Specifications

Description MC100LVEL39
Compliance Pb-free Halide free
Type Divider
Input Level ECL LVDS
Output Level ECL
VCC Typ (V) 3.3
fMax Typ (MHz) 1000
tpd Typ (ns) 1.05
tR & tF Max (ps) 550
Package Type SOIC-20W

Last 6 months Inventory & Pricing History

Alternative Descriptions

Clock Generator, 1Ghz, -40 To 85Deg C | Newark Electronics
MC Series 3.3 V Surface Mount ECL Clock Generation Chip - SOIC-20W | Future Electronics
IC: digital | TME
CLOCK GENERATOR, 1GHZ, -40 TO 85DEG C | Farnell

Frequently Asked Questions

Where can I find additional details, specifications and documents for a MC100LVEL39DWR2G?

Additional datasheets, footprints and schematics for MC100LVEL39DWR2G are listed on our Part Details page. You can also find images and similar parts to MC100LVEL39DWR2G on this page.

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What category does MC100LVEL39DWR2G fall under?

The MC100LVEL39DWR2G is listed under Timing, Logic & Memory > Clock & Data Distribution > Arithmetic Functions.

Can I view similar or alternative parts?

You can view similar parts to MC100LVEL39DWR2G when available in the Arithmetic Functions range under the specifications section at the bottom of the details page.

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Is the MC100LVEL39DWR2G RoHS compliant?

Yes. This part has been flagged as RoHS Compliant by ON Semiconductor.

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Authorised distributors including Rochester Electronics, Newark Electronics, Future Electronics, Avnet America and TME have stock available or on a lead time for MC100LVEL39DWR2G.

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