MC100LVEP210FARG Clock & Data Distribution by ON Semiconductor

Clock Driver, 1:5 Differential, Dual ECL / PECL / HSTL, 2.5 V / 3.3 V

Semiconductors - ICs
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Status: Active
Series: MC100LVEP210
RoHS: Compliant
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The MC100LVEP210 is a low skew 1-to-5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single ended if the VBB output is used. The signal is fanned out to 5 identical differential outputs. HSTL inputs can be used when the EP210 is operating in PECL mode. The LVEP210 specifically guarantees low output-to-output skew. Optimal design, layout, and processing minimize skew within a device and from device to device. To ensure the tight skew specification is realized, both sides of the differential output need to be terminated identically into 50 ohms even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew. The MC100LVEP210, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the LVEP210 to be used for high performance clock distribution in +3.3 V or +2.5 V systems. Single-ended CLK input operation is limited to a VCC ≤ 3.0 V in PECL mode, or VEE ≤ -3.0 V in ECL mode. Designers can take advantage of the LVEP210's performance to distribute low skew clocks across the backplane or the board. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies. For more information on using PECL, designers should refer to Application Note AN1406/D.

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Features

85 ps Typical Device-to-Device Skew
20 ps Typical Output-to-Output Skew
VBBOutput
Jitter Less than 1 ps RMS
350 ps Typical Propagation Delay
Maximum Frequency >3 Ghz
The 100 Series Contains Temperature Compensation
PECL and HSTL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -3.8 V
Open Input Default State
LVDS Input Compatible

Specifications

Description MC100LVEP210
Compliance Pb-free Halide free
Type Buffer
Channels 2
Input / Output Ratio 1:5
Input Level CML ECL HSTL LVDS
Output Level ECL
VCC Typ (V) 2.5 3.3
tJitterRMS Typ (ps) 0.207
tskew(o-o) Max (ps) 25
tpd Typ (ns) 0.35
tR & tF Max (ps) 250
fmaxClock Typ (MHz) 3000
Package Type LQFP-32

Last 6 months Inventory & Pricing History

Alternative Descriptions

Clock Driver, 3Ghz, -40 To 85Deg C | Newark Electronics
MC100LVEP210 Series 3.8 V 3 GHz 1:5 Dual Differential Clock Driver - LQFP-32 | Future Electronics
IC: digital | TME
CLOCK DRIVER, 3GHZ, -40 TO 85DEG C | Farnell

Frequently Asked Questions

Where can I find additional details, specifications and documents for a MC100LVEP210FARG?

Additional datasheets, footprints and schematics for MC100LVEP210FARG are listed on our Part Details page. You can also find images and similar parts to MC100LVEP210FARG on this page.

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What category does MC100LVEP210FARG fall under?

The MC100LVEP210FARG is listed under Timing, Logic & Memory > Clock & Data Distribution > Drivers & Fanout Buffers.

Can I view similar or alternative parts?

You can view similar parts to MC100LVEP210FARG when available in the Drivers & Fanout Buffers range under the specifications section at the bottom of the details page.

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Is the MC100LVEP210FARG RoHS compliant?

Yes. This part has been flagged as RoHS Compliant by ON Semiconductor.

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Authorised distributors including Rochester Electronics, Newark Electronics, Future Electronics, Avnet America and TME have stock available or on a lead time for MC100LVEP210FARG.

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