MC100LVEP34DTR2G Clock & Data Distribution by ON Semiconductor

2.5 V / 3.3 V ECL ÷2, ÷4, ÷8 Clock Generation Chip

Semiconductors - ICs
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Status: Active
Series: MC100LVEP34
RoHS: Compliant
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The MC100LVEP34 is a low skew DIV2, DIV4, DIV8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The common enable (ENbar) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock; therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon startup, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as multiple LVEP34s in a system. Single-ended CLK input operation is limited to a VCC of ≥ 3.0 V in PECL mode, or VEE ≤ -3.0 V in NECL mode.

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Features

35 ps Output-to-Output Skew
Synchronous Enable/Disable
Master Reset for Synchronization
The 100 Series Contains Temperature Compensation.
PECL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -3.8 V
Open Input Default State
LVDS Input Compatible

Specifications

Description MC100LVEP34
Compliance Pb-free Halide free
Type Divider
Input Level CML ECL LVDS
Output Level ECL
VCC Typ (V) 2.5 3.3
fMax Typ (MHz) 2800
tpd Typ (ns) 0.7
tR & tF Max (ps) 200
Package Type TSSOP-16

Last 6 months Inventory & Pricing History

Alternative Descriptions

CLOCK GENERATOR, 2.8GHZ, -40 TO 85DEG C | Farnell

Frequently Asked Questions

Where can I find additional details, specifications and documents for a MC100LVEP34DTR2G?

Additional datasheets, footprints and schematics for MC100LVEP34DTR2G are listed on our Part Details page. You can also find images and similar parts to MC100LVEP34DTR2G on this page.

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What category does MC100LVEP34DTR2G fall under?

The MC100LVEP34DTR2G is listed under Timing, Logic & Memory > Clock & Data Distribution > Arithmetic Functions.

Can I view similar or alternative parts?

You can view similar parts to MC100LVEP34DTR2G when available in the Arithmetic Functions range under the specifications section at the bottom of the details page.

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Is the MC100LVEP34DTR2G RoHS compliant?

Yes. This part has been flagged as RoHS Compliant by ON Semiconductor.

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