| Status: | Active |
|---|---|
| Series: | SPC58EG80E5 |
| RoHS: | Compliant |
| AEC-Q100 qualified |
| High performance e200z4 triple core: 32-bit Power Architecture technology CPU Core frequency as high as 180 MHz Variable Length Encoding (VLE) Floating Point, End-to-End Error Correction |
| 32-bit Power Architecture technology CPU |
| Core frequency as high as 180 MHz |
| Variable Length Encoding (VLE) |
| Floating Point, End-to-End Error Correction |
| 6582 KB (6144 KB code flash+ 256 KB data flash) on-chip flash memory: supports read during program and erase operations, and multiple blocks allowing EEPROM emulation Supports read while read between the two code Flash partitions. |
| supports read during program and erase operations, and multiple blocks allowing EEPROM emulation |
| Supports read while read between the two code Flash partitions. |
| 608 KB on-chip general-purpose SRAM (in addition to 160 KB core local data RAM): 64KB in CPU_0, 64 KB in CPU_1 and 32 KB in CPU_2 |
| 182 KB HSM dedicated flash memory (144 KB code + 32 KB data) |
| Multi-channel direct memory access controller (eDMA) one eDMA with 64 channels one eDMA with 32 channels |
| one eDMA with 64 channels |
| one eDMA with 32 channels |
| 1 interrupt controller (INTC) |
| Comprehensive new generation ASIL-D safety concept: ASIL-D of ISO 26262 One CPU channel in lockstep Logic BIST FCCU for collection and reaction to failure notifications Memory BIST Cyclic redundancy check (CRC) unit Memory Error Management Unit (MEMU) for collection and reporting of error events in memories |
| ASIL-D of ISO 26262 |
| One CPU channel in lockstep |
| Logic BIST |
| FCCU for collection and reaction to failure notifications |
| Memory BIST |
| Cyclic redundancy check (CRC) unit |
| Memory Error Management Unit (MEMU) for collection and reporting of error events in memories |
| Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters with end-to-end ECC |
| Body cross triggering unit (BCTU) Triggers ADC conversions from any eMIOS channel Triggers ADC conversions from up to 2 dedicated PIT_RTIs |
| Triggers ADC conversions from any eMIOS channel |
| Triggers ADC conversions from up to 2 dedicated PIT_RTIs |
| Enhanced modular IO subsystem (eMIOS): up to 64 timed IO channels with 16-bit counter resolution |
| Enhanced analog-to-digital converter system with: 4 independent fast 12-bit SAR analog converters One supervisor 12-bit SAR analog converter One standby 10-bit SAR analog converter |
| 4 independent fast 12-bit SAR analog converters |
| One supervisor 12-bit SAR analog converter |
| One standby 10-bit SAR analog converter |
| Communication interfaces: 18 LINFlexD modules 10 deserial serial peripheral interface (DSPI) modules 8 MCAN interfaces with advanced shared memory scheme and ISO CAN-FD support Dual-channel FlexRay controller Two independent Ethernet controllers 10/100Mbps compliant IEEE 802.3-2008 |
| 18 LINFlexD modules |
| 10 deserial serial peripheral interface (DSPI) modules |
| 8 MCAN interfaces with advanced shared memory scheme and ISO CAN-FD support |
| Dual-channel FlexRay controller |
| Two independent Ethernet controllers 10/100Mbps compliant IEEE 802.3-2008 |
| Low power capabilities Versatile low power modes Ultra low power standby with RTC Smart Wake-up Unit for contact monitoring Fast wakeup schemes |
| Versatile low power modes |
| Ultra low power standby with RTC |
| Smart Wake-up Unit for contact monitoring |
| Fast wakeup schemes |
| Dual phase-locked loops with stable clock domain for peripherals and FM modulation domain for computational shell |
| Nexus development interface (NDI) per IEEEISTO 5001-2003 standard, with some support for 2010 standard |
| Boot assist Flash (BAF) supports factory programming using a serial bootload through the asynchronous CAN or LIN/UART |
| Junction temperature range -40 °C to 150 °C |
Product Specifications |
|---|
| DS11758 32-bit Power Architecture microcontroller for automotive ASIL-D applications |
Reference Manuals |
|---|
| RM0004 Programmer's reference manual for Book E processors |
| RM0391 SPC58 E/G Line - 32 bit Power Architecture automotive MCU Triple z4 cores 180 MHz, 6 MBytes Flash, HSM, ASIL-D |
Presentations |
|---|
| SPC5 32-bit microcontroller Series featuring Power Architecture |
| SPC5 Family Overview October 2015 |
Selection Guides |
|---|
| SPC58 B/C/G-lines - Automotive MCUs for car body & security |
| MCU 32-Bit SPC58 e200z4 RISC 4MB Flash 1.14V to 1.26V 144-Pin TQFP T/R | Avnet America |
| MCU, AEC-Q100, 160MHZ, 32-BIT, TQFP-144 | element14 |
Where can I find additional details, specifications and documents for a SPC58EG80E5FEC0X?
Additional datasheets, footprints and schematics for SPC58EG80E5FEC0X are listed on our Part Details page. You can also find images and similar parts to SPC58EG80E5FEC0X on this page.
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What category does SPC58EG80E5FEC0X fall under?
The SPC58EG80E5FEC0X is listed under Automotive Microcontrollers > SPC5 32-bit Automotive MCUs > SPC5 General Purpose MCUs > SPC58 G Line MCUs.
Can I view similar or alternative parts?
You can view similar parts to SPC58EG80E5FEC0X when available in the SPC58 G Line MCUs range under the specifications section at the bottom of the details page.
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Is the SPC58EG80E5FEC0X RoHS compliant?
Yes. This part has been flagged as RoHS Compliant by STMicroelectronics.
Which authorised distributors for SPC58EG80E5FEC0X have stock available?
Authorised distributors including Avnet America, element14, EBV Elektronik and Avnet Silica have stock available or on a lead time for SPC58EG80E5FEC0X.
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